ECEn 485: Timing Synchronization for QPSK

Your previous QPSK Simulink Exercise assumed you knew the phase of the symbol clock at the transmitter (i.e. you knew where symbols begin and end). Unfortunately, this is not the case in practice. The symbol timing phase is unknown and must be extracted from the received signal using a symbol timing recovery subsystem.

In this exercise, you will design the symbol timing recovery subsystem for QPSK which will be used to process QPSK modulated data contained in the file qpsktrdata.mat. This is a multi-rate system where the sample clock and the data clock are not quite aligned and are said to be incommensurate.

Specifications

normalized symbol rate:
normalized carrier frequency:
carrier phase:
symbol clock offset:
pulse shape:

average energy:
input file:
packet format:

1/8 bit/sample (nominal)
0.3 cycles/sample (nominal)
0°
unknown!!
square-root raised cosine
roll-off = 0.5
Lp = 6
2 Watt-Seconds
qpsktrdata.mat
TR = 11 00 11 00 ... 11 00 (64 symbols)
SYNC = 11 10 10 11 10 01 00 00
DATA = 525 symbols (1050 bits)

Preliminary Design

The design should start with your design from the QPSK Exercise. The symbol timing synchronization subsystem is shown in blue in the figure below.

Design Notes:

1	The loop operates at 2 samples/symbol.

2	Use a Farrow filter for your interpolator. I used a piecewise-parabolic interpolation filter. You can use the same or the cubic interpolator. These structures are described in detail in Section 5.4.2 of the text.

3	For the timing error detector (TED) I suggest you use the zero-crossing timing error detector (ZCTED) as described in the Section 5.4.1 of the text. Note that the ZCTED operates at 2 samples/symbol.

4	Interpolation control is performed using a decrementing modulo-1 counter as described in Section 5.4.3 of the text.

The enabled hold block keeps the input value when the enable signal is 0 and accepts a new input when the enable signal is > 0. This block is needed since the fractional interval is updated by the mod-1 counter only once per symbol but the interpolator needs it 2 times per symbol. The hold operation ensures that the interpolator is using the proper value for the fractional interval.

Simulink provides skeletal enabled subsystems:

Simulink -> Ports & Subsystems -> Enabled Subsystem

The default enabled subsystem is shown below:

The subsystem consists of a simple wire with the enable icon above it. This means the wire is only active when the enable signal exceeds a predefined threshold (double click on the enable block to set the threshold). When the enable signal is below the predefined threshold, nothing happens and the output holds its value.

The only decisions that should be saved in the matlab workspace are those that correspond to valid data (that is, when enable = 1). Use an enabled subsystem similar to the one described in in the BPSK Timing Synchronization Simulink Exercise . You will have to modify the decision function to make QPSK decisions rather than BPSK decisions.

Design the timing phase detector and loop filter using blocks from the Simulink, Communications Blockset, and DSP Blockset libraries.

normalized bandwidth:
damping factor:

0.50% of the symbol rate
1

Exercise

1	Incorporate the symbol timing synchronization subsystem into a QPSK detector.

2	For an input to the detector, use the From File block with the Filename field set to `qpsktrdata.mat` and the Sample Time Field set to 1.

Set the simulation parameters as follows:

Start Time:
Stop Time:
Solver options

Fixed step size:

0.0
(64 + 8 + 525 + 26)*8
Type: Fixed-step
discrete (no continuous states)
auto

4	Run the simulation.

5	The detector produces a lot of decisions (the number depends on how your timing loop synchronized) .

6	To find the data symbols, look for the 8 symbol SYNC pattern in the detector output. Once you find it, the following 525 symbols correspond to 150 7-bit ASCII characters.

7	Plot the phase error (loop filter input) for the timing PLL and use this plot to estimate how long (measured in symbols) it took for the PLL to phase lock. Either attach the plot to your email message (preferred method) or print it out and turn it in to the simulink TA.

8	Plot the interpolation interval (mu) as a function of time. Either attach the plot to your email message (preferred method) or print it out and turn it in to the simulink TA.

9	Determine the message contained in the modulated data by using your script or the on-line ASCII table.

10	Email your answer to ee485ta@ee.byu.edu. Attach to your email message, the simulink model file (.mdl) that contains your detector design and the plots (if you turn them in that way).

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