The data in the file oqpskcrdata.mat was produced using the OQPSK modulator shown in the first OQPSK Simulation Exercise except for two important differences:

The detector design should start with the OQPSK detector from the previous OQPSK Simulink Exercise with the addition of the carrier phase synchronization subsystem as illustrated below.


The system requires a commutator. The data samples arrive at the input at a rate equivalent to 2 samples/symbol and are output in two parallel streams at a symbol rate equivalent to 1 sample/symbol. The commutator may be constructed in Simulink using a pair of downsample blocks with different sample offsets and a delay as shown below. (The delay is required to properly align the even- and odd-indexed samples.)


Note that the loop filter and DDS operate at 2 samples/symbol. Since the phase detector operates at 1 sample/symbol, the phase detector output is upsampled by 2 (by inserting a zero) prior to being filtered by the loop filter.

Design the phase detector and loop filter using blocks form the Simulink, Communications, and DSP Blockset libraries. I used the following settings in my design (these values are normalzed to the symbol rate):Important Hint: Care must be taken to ensure that the commutators outputs are properly aligned with the indices required by the phase error detector and the decision subsystem.