ECEn 485: Phase Shift Keying

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Phase Shift Keying

ECEn 485: Phase Shift Keying

In this exercise, you will design a BPSK detector to process the BPSK modulated data contained in the file bpskdata.mat

[image]

normalized symbol rate:
normalized carrier frequency:
carrier phase:
symbol clock offset:
pulse shape:
average energy:
input file:
input message length:

1/8 bit/sample
0.25 cycles/sample sec
0°
0 sec
SRRC (roll-off = 50%, Lp = 6 symbols)
1 Joule
bpskdata.mat
154 symbols (bits)

Preliminary Design

Design the Detector

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Design the BPSK detector using blocks from the SIMULINK Block Library and the Communications Blockset Library.

Test the Detector Design

Test your design using the following procerure:

Design a modulator (below) to meet the above specifications except make the input the four symbol sequence 1 0 0 1

[image]

2	Connect the output of your modulator to the the input of your detector.

3	Connect the output of your detector to a To Workspace block. (Be sure to open the Properties Dialog Window and set the Save format to matrix.)

Set the simulation parameters as follows:

Start Time:
Stop Time:
Solver options

Fixed step size:

0.0
(12+4+1)*8
Type: Fixed-step
discrete (no continuous states)
1

Note: The stop time is computed as follows: 12 = 2*Lp (the delay of the pulse shaping filter plus the delay of the matched filter) ; 4 = the number of data symbols; 1 = the one bit (or symbol) delay to allow proper phasing of the downsample operation in the detector; 8 = the number of samples/symbol.

5	Run the simulation and plot the received signal r[n] and the matched filter output on the same set of axes.

6	Adjust the delay on the Downsample block to obtain the correct sybmol timing.

7	Does the workspace variable agree with the input sequence (`1 0 0 1`)?

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