ECEn 485: Carrier Phase Synchronization for OQPSK

In the previous OQPSK Simulink Exercise the carrier phase was assumed known. In practice, the carrier phase is unknown and must be estimated from the received signal using a carrier phase estimator. In this exercise, you will design a carrier phase synchronizator for Offset-QPSK based on a discrete-time phase-locked loop. The system will be used to process the data contained in the file oqpskcrdata.mat.

The carrier phase error detector for non-offset QPSK possessed a 90-degree phase ambiguity. For Offset-QPSK, the carrier phase error detector possesses a 180-degree phase ambiguity. However, for Offset-QPSK, an additional ambiguity exists. It will not be known which sample index corresponds to the inphase component and which sample corresponds to the delayed quadrature component. Thus a differential encoder/encoder must account for this additional ambiguity. In this exercise, such a differential encoding is used.


Specifications

modulation:                   OQPSK
pulse shape:                  HS
average energy:               2 Watt-seconds
normalized symbol rate:       1/20 symbol/sample
normalized carrier frequency: 0.3 cycles/sample
carrier phase:                unknown
symbol clock offset:          0 sec
input file:                   oqpskcrdata.mat
ambiguity resolution:         differential encoding (described below)
packet format:                SYNC = 00 00 00 00 00 00 00 00
                              DATA = 434 symbols (868 bits)

This packet is repeated approximately 3 times


Introduction

The data in the file oqpskcrdata.mat was produced using the OQPSK modulator shown in the first OQPSK Simulink Exercise except for two important differences:

Preliminary Deisgn

The detector design should start with the OQPSK detector from the previous OQPSK Simulink Exercise with the addition of the carrier phase synchronization subsystem as illustrated below.

Note that unlike the detector in the previous exercise, that inphae and quadrature matched filter outputs are both sampled at 2 samples/symbol.

The detector requires a commutator which can be thought of as a serial-to-parallel converter. The data samples arrive at the input at a rate equivalent to 2 samples/symbol and are output in two parallel streams at a symbol rate equivalent to 1 sample/symbol. The commutator may be constructed in Simulink using a pair of downsample blocks with different sample offsets as shown below.

Note that the loop filter and DDS operate at 2 samples/symbol. Since the phase detector operates at 1 sample/symbol, the phase detector output is upsampled by 2 (by inserting a zero) prior to being filtered by the loop filter.

Design the phase detector and loop filter using blocks form the Simulink, Communications, and DSP Blockset libraries. I used the following settings in my design (these values are normalzed to the symbol rate):

normalized bandwidth: 0.05
damping factor:       1

Important Hint: Care must be taken to ensure that the commutators outputs are properly aligned with the indices required by the phase error detector and the decision subsystem.

Exercise

  1. Design an OQPSK detector with a carrier phase syncrhonization subsystem using blocks from the SIMULINK Block Library and the Communications Blockset.

  2. Connect the From File block to the input of your detector and set the Filename to oqpskcrdata.mat

  3. Set the simulation parameters as follows:
        Start time      0.0
        Stop time       (8+434+2)*20*3
            Solver options          Fixed-step
                                    discrete (no continuous states)
            Fixed-step size:        1   

  4. Run the simulation.

  5. The detector produces 1333 symbol estimates. Convert the symbols to 2666 bits and apply the differential decoding rule specified above.

  6. 868 of the 2666 differential decoded bits correspond to the 124 7-bit ASCII characters that form the DATA field. (Actually, this data sequence occurs three times, but your carrier phase PLL may not lock in time for you to identify the first occurrence.) Use the SYNC pattern to identify the beginning of the data field.

  7. Determine the message using your matlab script or the on-line ASCII table.

  8. email your answer and the file oqpskout.dat to ee485ta@ee.byu.edu. Attach to your email message, the simulink model file (.mdl) that contains your detector design.

  9. Plot the phase error for the PLL and use the plot to estimate how long (measured in symbols) it took for your PLL to lock. Print this plot and turn it in to the Simulink TA.

Back to the ECEn 485 Simulink Exercise Page.
Created by Michael Rice
mdr@ee.byu.edu
Last modified: 26 Oct 2004